Semiconductor device and its manufacturing method

ABSTRACT

There has been a problem that micromiaturization causes increase of the resistance of wiring structure and degradation of electron migration resistance and stress migration resistance. The present invention provides a wiring structure of a semiconductor device having a low resistance even when the semiconductor device is microminiaturized, free of electron migration and stress migration, and having a high reliability and a method for manufacturing the same. A semiconductor device having a wiring or a connection plug made of a mixture of a metal and carbon nanotubes berried in a wiring groove or a via hole made in an insulating film on a substrate where a semiconductor chip is fabricated, and its manufacturing method are provided.

TECHNICAL FIELD

The present invention relates to a semiconductor device and a method ofmanufacturing the semiconductor device and, more particularly, to asemiconductor device having a connection plug or an interconnection anda method of manufacturing the semiconductor device.

BACKGROUND ART

In a connection plug that connects interconnection materials orinterconnections of a semiconductor device, low-resistance metals suchas Cu or Al are used. With the scale down design of semiconductordevices moving ahead, the cross sections of interconnections andinterconnection plugs decrease. As a result, the following phenomenahave become more serious:

(1) Increase in the resistance values of interconnections and connectionplugs

(2) Electromigration of metal ions by current densities which haveincreased and

(3) Stress migration due to heat cycles during manufacturing and heatgeneration etc. during working.

Electromigration and stress migration pose problems, such as changeswith time in the resistance of metal interconnections and connectionplugs and disconnections of them.

In order to prevent interconnections from being broken due toelectromigration, there is available a method which involves using twomaterials in combination: an interconnection material A which has a lowresistance value but is not resistant to migration (for example, Cu orAl) and an interconnection material B which has a high resistance valuebut is resistant to migration (for example, titanium, tungsten andsuicide materials of these metals). In this case, the disconnection ofinterconnections can be prevented by the redundancy effect of theinterconnection material B. However, this method is effective forinterconnections although it is not effective for connection plugs.Also, although interconnections do not lead to disconnections, there isa problem that the interconnection resistance increases. Furthermore,this method is not effective for stress migration.

In contrast, there has been proposed a semiconductor device element inwhich carbon nanotubes having resistance to electromigration are used inconnection plugs (Japanese Journal of Applied Physics, Vol. 41, pp. 4370to 4374, 2002).

In this example, carbon nanotubes are formed in via holes and used asconnection plugs that connect an upper interconnection layer and a lowerinterconnection layer together. Approximately 1000 carbon nanotubes areformed in a via hole of 5×30 micrometers square.

It is known that carbon nanotubes have high migration resistance andhence migration does not readily occur in carbon nanotubes.

When methods that involve combining interconnection materials areadopted, it is impossible to prevent the occurrence of voids due to theelectromigration in connection plugs. Also, in interconnections, it isimpossible to prevent changes in resistance that are caused of thedisconnection of part of the interconnections due to electromigration orstress migration.

However, the reason why connection plugs formed from multilayer carbonnanotubes have high resistance values in spite of the fact that themultilayer carbon nanotubes have metallic properties and low resistanceis that the contact resistance between the carbon nanotubes and themetal interconnections is high, with the result that the resistance ofconnection plugs increases due to the contact resistance even when theresistance of the carbon nanotubes is low.

The present invention provides an interconnection structure of ahigh-reliability semiconductor device which has a low resistance valueeven in the case of scale down design and does not produceelectromigration and stress migration, and a method of manufacturing theinterconnection structure.

DISCLOSURE OF THE INVENTION

According to the present invention, it is possible to provide asemiconductor device having an interconnection structure resistant toelectromigration and stress migration.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic sectional view to show an interconnectionstructure in the first embodiment of the present invention;

FIGS. 2(a) to 2(c) are each a schematic sectional view to explain eachstep of a manufacturing method of an interconnection in the firstembodiment of the present invention;

FIG. 3 is a schematic sectional view to show an interconnectionstructure by the single damascene process in the second embodiment ofthe present invention;

FIGS. 4(a) to 4(g) are each a schematic sectional view to explain eachstep of a manufacturing method of an interconnection by the singledamascene process in the second embodiment of the present invention;

FIG. 5 is a schematic sectional view to show the structure of aconnection plug by the single damascene process in the second embodimentof the present invention;

FIGS. 6(a) to 6(g) are each a schematic sectional view to explain eachstep of a manufacturing method of a connection plug by the singledamascene process in the second embodiment of the present invention;

FIG. 7 is a schematic sectional view to show an interconnection and aconnection plug by the dual damascene process in the third embodiment ofthe present invention; and

FIGS. 8(a) to 8(h) are each a schematic sectional view to show each stepof a manufacturing method of an interconnection and a connection plug bythe dual damascene process in the third embodiment of the presentinvention.

The reference numerals used in the drawings will be described below.

The numeral 10 denotes an insulating film, the numerals 11, 51 aninterconnection, the numerals 12, 29, 42, 49, 52 an interlayerdielectric film, the numerals 13, 28, 43, 48 a barrier metal layer, thenumerals 14, 24, 44 a carbon nanotube, the numerals 17, 55 aninterconnection trench, the numerals 15, 25, 45 a particle, the numerals18, 32, 57 a seed layer, the numerals 19, 33, 39, 58 a metal layer, thenumerals 26, 46 a connection plug, the numerals 16, 27, 30, 47, 50, 53an etching stopper layer, the numerals 31, 56 a via hole, the numeral 54a hole, the numerals 34, 59 a first interconnection layer, the numerals35, 60 a connection plug layer, and the numeral 61 a secondinterconnection layer.

BEST MODE FOR CARRYING OUT THE INVENTION

The present invention provides an interconnection structure best suitedto a semiconductor device which is manufactured according to a designrule with a line and space of not more than 0.1 μm. In the presentinvention, there is provided a semiconductor device in which ananomaterial is substantially uniformly disposed in a section of aconnection plug formed from a metal and, furthermore, a nanomaterial issubstantially uniformly formed on a bottom surface of an interconnectionformed from a metal.

The nanomaterial is a fibrous carbon nanomaterial, a particle-likecarbon nanomaterial or a thin silicon wire.

These nanomaterials are oriented substantially perpendicularly to asubstrate. Furthermore, it is preferred that these nanomaterials bedisposed in the whole connection plug, and in the case of aninterconnection, it is preferred that the nanomaterial be provided up tothe vicinity of a top surface of the interconnection.

Furthermore, it is advantageous in terms of voids when the metal isformed by an MOCVD method or a plating method.

As a first manufacturing method, there is provided a method ofmanufacturing a semiconductor device which comprises the step of forminga metal of nanometer size on an insulating base, the step of causing ananomaterial to grow on the metal of nanometer size, the step ofdepositing the metal on the substrate on which the nanomaterial hasgrown, and the step of working the metal including the nanomaterial intoan interconnection.

As a second manufacturing method, a semiconductor device can bemanufactured by the following steps. That is, there is provided a methodof manufacturing a semiconductor device which comprises the step offorming a trench in an insulating base, the step of forming a metal ofnanometer size at least on a bottom of the trench, the step of causing ananomaterial to grow on the metal of nanometer size, the step ofdepositing the metal so that the trench is embedded with the metal, andthe step of working the metal including the nanomaterial into aninterconnection.

In this case, the insulating base may have an interconnection in a lowerlayer or a device element formed on the semiconductor substrate and atleast part of the lower-layer interconnection or the element may beexposed to part of the bottom of the trench formed in the insulatingbase.

The metal of nanometer size becomes a nucleus which causes thenanomaterial to grow, and the metal of nanometer size is any of iron,platinum, nickel, cobalt or silicide substances of nickel and cobalt,and iron oxides.

The nanomaterial is a fibrous carbon nanomaterial, a particle-likecarbon nanomaterial or a thin silicon wire.

In the step of depositing the metal, it is advantageous to deposit themetal by a plating method or an MOCVD method in terms of voids.

EMBODIMENTS OF THE PRESENT INVENTION WILL BE DESCRIBED

When an excessive current is caused to flow through an interconnectionand a connection plug which are formed from a metal alone,electromigration occurs, which is a phenomenon that metal ions migrateon an electron flow. On the other hand, if a nanomaterial having highmechanical strength, such as a carbon nanotube, for example, is presentin a place to which metal ions migrate, the migration of the metal ionsis suppressed. That is, electromigration is suppressed.

In metals having low electric resistance used in the interconnectionsand connection plugs of present semiconductor device elements, such asgold, silver, copper and aluminum, atoms thereof are bonded by metallicbonds. In contrast, the atoms that constitute nanomaterials, such as afullerene, a carbon nanotube, a carbon nanohorn and a thin silicon wire,are bonded by covalent bonds.

Carbon materials having such a structure that only the leading end of acarbon nanotube protrudes from a carbon aggregate, such as the carbonnanohorn disclosed in the Japanese Patent Laid-Open No. 2001-64004, havebeen manufactured or discovered as one form of carbon nanomaterial.

Because carbon nanomaterials are formed from covalent bonds, which havehigher bonding strength than metallic bonds, separation requires greatenergy. Therefore, covalent bonds have higher mechanical strength andelectromigration resistance than metallic bonds.

Table 1 shows a comparison of mechanical strength and Young's modulusbetween conventionally used Cu and Al and a carbon nanotube. TABLE 1Electric resistivity Young's modulus Material (×10⁻⁶ Ωcm) (×10¹² Pa) Al2.74 0.068 Cu 1.70 0.126 Carbon Nanotube <0.1 ˜1

Carbon fibers represented by a single-layer carbon nanotube and amultilayer carbon nanotube, carbon materials represented by a fullerene,a carbon nanohorn, etc., and a thin silicon wire can be enumerated asnanomaterials.

It is necessary only that carbon nanotubes have a diameter of not morethan 100 nm and an aspect ratio of not less than 10.

A thin silicon wire is a fibrous material made of silicon having adiameter of 1 to 100 nm and an aspect ratio of not less than 10.

Among these nanomaterials, particularly, fibrous materials have thefunction of preventing the breakage of connection plugs andinterconnections that occur due to mechanical stress and temperaturestress during manufacture. Because fibrous structures having highmechanical strength are contained in the metals that constituteconnection plugs and interconnections, as with the relationship betweenreinforcing bars and concrete in a building, fibrous structures(reinforcing bars) increase the strength of a metal (the framework of abuilding) and protect connection plugs and interconnections (thebuilding) from vibrations from outside and thermal shrinkage.

In the case of a carbon nanotube, a multilayer carbon nanotube exhibitsmetallic properties. On the other hand, by selecting chirality, whichshows how a carbon sheet is wound, a single-layer carbon nanotubeexhibits metallic properties and its resistivity becomes very small.

The resistivity of a carbon nanotube in the case that it exhibitsmetallic properties is shown in Table 1.

When chirality becomes different, a single-layer carbon nanotubeexhibits metallic properties or semiconducting properties. Although itis difficult to control chirality with the current techniques, thesuperiority of the present invention is not demolished even when asemiconducting single-layer carbon nanotube is contained at anappropriate ratio. This is because the connection plug andinterconnection of the present invention are formed from a mixedmaterial of a carbon nanotube and a metal and an increase in resistancecan be prevented by the fact that a current flows through the metalpart. Also, because the surface of a carbon nanotube is covered with themetal, the contact resistance of the connection plug and theinterconnection can be reduced.

The carbon nanotube used in the present invention may be either amultilayer carbon nanotube or a single-layer carbon nanotube. Amultilayer carbon nanotube can be easily formed by the CVD method.Furthermore, carbon nanotubes are not subject to constraints onquantification by being a thin wire and, therefore, carbon nanotubeshave the advantage that they have always metallic properties.

Next, embodiments of the present invention will be described in detailwith reference to the drawings.

First Embodiment

The description will be given by using FIG. 1 that is a schematicsectional view of an interconnection structure in a semiconductor deviceof the first embodiment.

In FIG. 1, an interconnection 11 is constituted by a metal layer 39,which is formed on an insulating film 10 formed on a semiconductorsubstrate (not shown) on which a device element or an interconnection isformed. Carbon nanotubes 14 are mixed in the metal layer 39 whichconstitutes the interconnection 11. The carbon nanotube 14 is formed ona particle 15 of nickel formed on the insulating film 10. The particle15 acts as a catalyst during the growth of the carbon nanotube, and thecarbon nanotube 14 grows, with the particle 15 serving as a nucleus.

A manufacturing method of a semiconductor device of the first embodimentwill be described with reference to FIGS. 2(a) to 2(c).

(Formation of Substrate and Formation of Carbon Nanotubes)

The insulating film 10 is formed on a silicon substrate (not shown) onwhich a semiconductor device element is formed.

The insulating film 10 is a film having a film thickness of 20 nm formedby the thermal oxidation method or the CVD method, and this is a filmformed from an oxide film, a nitride film, an oxynitride film, etc.

Next, particles 15 are formed on the insulating film 10 by using Nihaving a film thickness of 2 to 10 nm formed by the sputtering method.

After that, carbon nanotubes 14 are caused to grow on the particles 15,with the particles 15 serving as nuclei (FIG. 2(a)).

The particle 15 is in the form of a granule of nanometer size, andmetals, metal suicides and metal oxides can be used. Iron, platinum,cobalt or silicide substances of cobalt and nickel or oxides, etc. arealso known in addition to nickel.

The granular particle 15 of nanometer size is obtained by forming a filmof 2 to 10 nm. The evaporation method and the chemical vapor depositionmethod may be used in addition to the sputtering method.

The carbon nanotube 14 may be fibrous carbon nanomaterials representedby a single-layer carbon nanotube, a multilayer carbon nanotube, etc.,granular carbon nanomaterials represented by a carbon nanohorn and afullerene, and a thin silicon wire.

The carbon nanotube is caused to grow by the thermal CVD method or theplasma CVD method. When the thermal CVD method is used, the nanotubetends to come to an entangled condition. In order to increase thestrength of an interconnection, the nanotube is advantageous when it isin an entangled condition.

On the other hand, when the plasma CVD method is used, it is possible tocause the carbon nanotube to be oriented perpendicularly to thesubstrate.

Growth conditions by the plasma CVD method are exemplified below:

Process gas: Mixed gas of acetylene and ammonia

Gas pressure: 3 to 20 torr

Substrate temperature: 400 to 500 degrees

DC power: 100 to 200 W

Growth conditions by the thermal CVD method are exemplified below:

Process gas: Methane

Gas pressure: 0.1 to 1 atm

Growth temperature: 500 to 800 degrees

(Formation of Interconnection)

An Al—Cu alloy (cu 5%), which is an Al-based alloy, was deposited as themetal layer 39 by the sputtering method on the insulating film 10 in afilm thickness of 600 nm (FIG. 2 (b)).

The metal layer 39 may be formed from Al, Cu, Ag, Al-based alloys (forexample, Al—Si, Al—Si—Cu, etc.), Cu-based alloys (Cu—Ag etc.) and thelike. The plating method and the MOCVD (metal organic chemical vapordeposition) method may be used in addition to the sputtering method.

There is a correlation between the density of carbon nanotubes and thefrequency of occurrence of voids during the deposition of the metallayer 39, and the higher the density, the higher the frequency ofoccurrence of voids. Voids may sometimes burst due to thermal expansion,thereby lowering the reliability of a semiconductor device. The growthof voids must be suppressed.

Voids can be suppressed by (1) a method which involves causing carbonnanotubes to be perpendicularly oriented and (2) a method which involveslowering the density of carbon nanotubes. The two methods (1) and (2)may be used in combination.

The density of carbon nanotubes can be controlled by changing the filmthickness of Ni or the like. The density of carbon nanotubes is lowered,for example, by reducing the film thickness of Ni.

Lastly, the interconnection 11 is formed by using a lithographytechnique and an etching technique which are publicly known (FIG. 2(c)).

In the case of this first embodiment, the stress migration resistanceincreases when the carbon nanotubes in the interconnection are providedup to the vicinity of a top surface of the interconnection. On the otherhand, when the carbon nanotubes are substantially uniformly provided onthe bottom surface, this is effective for the resistance toelectromigration. Therefore, a granular carbon nanomaterial such as acarbon nanohorn may be used.

Second Embodiment

The second embodiment of the present invention is an interconnectiontrench structure by the single damascene process.

FIG. 3 shows an interconnection structure by the single damasceneprocess.

The interconnection structure by the single damascene process will bedescribed. There are formed an insulating film 10, which is formed on asemiconductor substrate (not shown) on which a device element or aninterconnection is formed, an interlayer dielectric film 12 formed onthe insulating film 10, and an etching stopper layer 16.

An interconnection 11 is formed in a trench which is formed in theinterlayer dielectric film 12 and the etching stopper layer 16. Theinterconnection 11 has particles 15 formed on a barrier metal layer 13and carbon nanotubes 14 which are caused to grow on the particles 15,and is embedded with a metal layer 39.

The particle 15 may be formed from Fe or Ni and the carbon nanotube 14may be formed from a carbon fiber, such as a carbon nanotube, a thinsilicon wire, etc.

Next, a method of manufacturing an interconnection structure by thesingle damascene process will be described with reference to FIGS. 4(a)to 4(g).

(Formation of Interconnection Trench 17)

The insulating film 10, the interlayer dielectric film 12 formed on theinsulating film 10, and the etching stopper layer 16 formed from SiC(film thickness 30 nm) by the plasma CVD method on the interlayerdielectric film 12 are formed on a silicon substrate (not shown) onwhich a semiconductor device element is formed. The etching stopper film16 works also as a diffusion preventing film that prevents a metal whichbecomes an interconnection from diffusing into the insulating film.

The insulating film 10 (film thickness 300 nm) may be an oxide filmformed by the thermal oxidation of the silicon substrate or an oxidefilm, a nitride film and an oxynitride film formed by the CVD method(the chemical vapor deposition method).

The interlayer dielectric film 12 (film thickness 600 nm) may be asilicon oxide film, a silicon nitride film and a silicon oxynitride filmformed, for example, by the CVD method or may be an organic substancehaving low permittivity and high voltage resistance, such asdivinylsiloxane benzocyclobutene which is disclosed in the JapanesePatent Laid-Open No. 2002-118169, for example. Because interconnectionintervals have narrowed due to scale down design, research on organicmaterials having low permittivity and high voltage resistance has beenwidely conducted in order to lower the interconnection capacitance.

It is preferred that the etching stopper layer 16 have a higher etchingrate than the interlayer dielectric film, and furthermore, it isnecessary for the etching stopper layer to work also as a diffusionpreventing film which prevents metal atoms from diffusing into theinsulating film. A silicon nitride film, a silicon oxynitride film, etc.are preferable as the etching stopper layer in addition to SiC (FIG. 4(a)).

After that, an interconnection trench 17 is formed by using alithography technique and an etching technique which are publicly known(FIG. 4 (b)).

(Formation of Barrier Metal)

Ta having a film thickness of 50 nm is formed by the sputtering methodas a barrier metal layer 13 on the whole surface of the substrate 10including the interconnection trench 17 (FIG. 4 (c)).

The barrier metal layer 13 is a film which prevents metal atoms fromdiffusing into the insulating film. Ti, TiN or a two-layer structure ofTi and TiN (Ti being a lower layer) or Ta, TaN or a two-layer structureof Ta and TaN (Ta being a lower layer) and the like are preferable.

(Formation of Carbon Nanotubes)

In the same manner as in the first embodiment, particles 15 are formedin a bottom portion of the interconnection trench 17 by using Ni havinga film thickness of 2 to 10 nm formed by the sputtering method. Afterthat, carbon nanotubes are formed on the particles 15, with theparticles 15 serving as nuclei. The carbon nanotubes are caused to growto such an extent that they protrude from the interconnection trench 17(800 nm or so) (FIG. 4 (d)).

(Formation of Interconnection)

Cu having a film thickness of 50 nm is formed as a seed layer 18 (FIG. 4(f)), a metal layer 19 of 650 nm formed from Cu is deposited by theplating method, and the metal layer having a total thickness of 700 nmformed from a Cu layer is formed on the barrier metal layer 13.

The MOCVD method (the metal organic chemical vapor deposition method)may be used in the formation of the seed layer 18.

When the metal layer 19 is formed by the MOCVD method (the metal organicchemical vapor deposition method), the formation of the seed layer 18may be omitted.

Voids are less apt to occur in the plating method and the MOCVD methodthan in the sputtering method.

The interconnection 11 is constituted by the seed layer 18 and the metallater 19.

In the case of trench interconnection, Cu and Ag or Cu-based alloys(Cu—Ag etc.), Ag-based alloys (Ag—Cu etc.), etc. are more frequentlyused than Al and Al-based alloys.

Lastly, excess Cu layers, carbon nanotubes and Ni other than those inthe interconnection trench 17 are removed by use of the publicly knownCMP method (the chemical mechanical polishing method) and theinterconnection 11 is formed. In the CMP method, a polishing solution (aslurry) obtained by mixing hydrogen peroxide with an abrasive, the maincomponent of which is silica, is used (FIG. 4 (g)).

The seed layer 18 may have the same composition as the metal layer 19 ormay have a different composition from that of the metal layer.

Next, the structure of a connection plug that connects a lower-layerinterconnection and an upper-layer interconnection together will bedescribed by using drawings.

There is provided a connection plug layer 35 which connects aninterconnection 11 formed in a first interconnection layer 34 (which isformed in the interlayer dielectric film 12).

The structure of a connection plug which connects with theinterconnection 11 of the lower layer will be described with referenceto FIG. 5.

In FIG. 5, the same numerals are given to the same parts as used in FIG.3.

Incidentally, although carbon nanotubes are not mixed in theinterconnection 11 of FIG. 5, carbon nanotubes 14 may be mixed as shownin FIG. 3.

The first interconnection layer 34 is constituted by the interlayerdielectric layer 12, the interconnection 11, the barrier metal layer 13,and etching stopper layers 16 and 27.

The connection plug 35 on the first interconnection layer 34 isconstituted by an interlayer dielectric film 29, a connection plug 26, abarrier metal layer 28, particles 25 and an etching stopper layer 30.Carbon nanotubes 24 are mixed in the connection plug 26.

In FIG. 5, an upper-layer interconnection to be connected to theconnection plug is not formed. However, the upper-layer interconnectioncan also be formed by the same manufacturing method as in FIGS. 4(a) to4(g).

Because structures having high mechanical strength and high resistanceto electromigration such as carbon nanotubes are contained in theconnection plug, electromigration does not occur even when structureshaving high mechanical strength and high resistance to electromigrationsuch as carbon nanotubes are not contained in the upper-layerinterconnection or the lower-layer interconnection.

On the other hand, it is effective for stress migration to mixstructures having high mechanical strength in the metal from which aninterconnection is formed.

A manufacturing method of a connection plug of an interconnectionstructure in the second embodiment will be described below withreference to FIGS. 6(a) to 6(g).

(Formation of First Interconnection Layer and Via Hole)

The insulating film 10 formed on a silicon substrate (not shown) onwhich a semiconductor device element is formed, the interlayerdielectric film 12 formed on the insulating film 10, and theinterconnection 11 formed in a trench portion, which is formed in theinterlayer dielectric film 12 formed on the insulating film 10 and thisfirst interlayer dielectric film 12 are formed from the barrier metallayer 13 and a metal. The etching stopper layers 16 and 27 are formed onthe interlayer dielectric film 12. The interlayer dielectric film 29 andthe etching stopper layer 30 are formed on the etching stopper layer 16(FIG. 6 (a)).

The interlayer dielectric film 29 is formed in the same manner as theinterlayer dielectric film 12.

After that, a via hole 31 is formed by using a photolithographytechnique and an etching technique which are publicly known (FIG. 6(b)).

(Formation of Barrier Metal)

In the same manner as with the trench interconnection, Ta having a filmthickness of 10 to 30 nm is formed as the barrier metal layer 28 by thesputtering method on the whole surface of the substrate including thevia hole 31 (FIG. 6 (c)).

(Formation of Carbon Nanotubes)

Ni which becomes the particles 25 and the carbon nanotubes 24 areformed. The carbon nanotubes are caused to grow to such an extent thatthey protrude from the via hole 31 (800 nm or so) (FIG. 6 (d)).

(Formation of Interconnection)

Cu having a film thickness of 30 nm is formed as a seed layer 32(FIG.6(e)), a metal layer 33 of 670 nm formed from Cu is deposited by theplating method, and a Cu layer having a total thickness of 700 nm isformed on the Ta film (FIG. 6(f). The MOCVD method (the metal organicchemical vapor deposition method) may be used in the formation of theseed layer and the Cu layer. Lastly, excess Cu layers, carbon nanotubesand Ni other than those in the via hole are removed by use of the CMPmethod, which is a conventional technique, and the connection plug 26 isformed (FIG. 6(g)).

The connection plug 26 can be manufactured in the same manner as withthe interconnection 11 described in FIGS. 4(a) to 4(g).

Third Embodiment

(Formation of Carbon Nanotubes)

Ni which becomes the particles 45 and carbon nanotubes 44 are formed.The carbon nanotubes 44 are caused to grow to such an extent that theyprotrude from the via hole 56 (800 nm or so) (FIG. 8 (e)).

(Formation of Interconnection and Connection Plug)

Cu having a film thickness of 30 nm is formed as a seed layer 57 (FIG.8(f)), a metal layer 58 of 1370 nm formed from Cu is deposited by theplating method, and a Cu layer having a total thickness of 1400 nm isformed on the Ta film (FIG. 8(g)). The MOCVD method (the metal organicchemical vapor deposition method) may be used in the formation of theseed layer and the Cu layer.

The suppression of the occurrence of voids can be performed by themethod described above.

Lastly, excess Cu layers, carbon nanotubes and Ni other than those inthe via hole 55 are removed by use of the CMP method (the chemicalmechanical polishing method), which is a conventional technique, and theinterconnection 51 and the connection plug 46 are formed (FIG. 8(h)).

Fourth Embodiment

In the first to third embodiments, particles which become nuclei areformed on the bottom surface of a trench or a via which becomes aninterconnection, carbon nanotubes are caused to grow on the nuclei andafter that, a metal film is formed, whereby a trench interconnectionstructure is formed.

In this embodiment, after the formation of a trench which becomes aninterconnection and the formation of a barrier metal layer, for example,in FIG. 4(c), an interconnection containing carbon nanotubes is formedby the

In the third embodiment, a description is given of a trenchinterconnection structure by the dual damascene process in which aninterconnection and a connection plug are simultaneously formed.

An interconnection structure by the dual damascene process will bedescribed with reference to FIG. 7.

Also in FIG. 7, the same numerals are given to the same parts as used inFIGS. 3 and 5.

Incidentally, although carbon nanotubes are not mixed in theinterconnection 11 of FIG. 7, carbon nanotubes 14 may be mixed as shownin FIG. 3.

A first interconnection layer 59 is constituted by an interlayerdielectric layer 12, an interconnection 11, a barrier metal layer 13,and etching stopper layers 16 and 47.

This embodiment provides, on an insulating film 10 formed on a substrate(not shown) including a semiconductor device element, the firstinterconnection layer 59, a connection plug 60 and a secondinterconnection layer 61. The first interconnection layer 59 isconstituted by the interlayer dielectric layer 12, the interconnection11, the barrier metal layer 13, and the etching stopper layers 16 and47.

The connection plug 60 on the first interconnection structure isconstituted by an interlayer dielectric film 49, a connection plug 46, abarrier metal layer 48, particles 45 and an etching stopper layer 50.Carbon nanotubes 24 are mixed in the connection plug 46.

The second interconnection layer 61 is constituted by an interlayerdielectric film 52, an interconnection 51, a barrier-metal layer 48, andan etching stopper layer 53. Carbon nanotubes 44 are mixed in theinterconnection 51.

A manufacturing method by the dual damascene process, which is the thirdembodiment of the present invention, will be described below withreference to FIGS. 8(a) to 8(h).

(Formation of First Interconnection Layer and Via Hole)

The first interconnection layer 59 excluding the etching stopper layer47 is formed by using the same method as used in the second embodiment.

Next, the etching stopper layers 47, 51, 53, each formed from an SiCfilm having a film thickness of 30 nm, are formed and the interlayerdielectric film 49, 52 formed from a silicon oxide film having a filmthickness of 600 nm are formed by the plasma CVD method in order:etching stopper layer 47, interlayer dielectric film 49, etching stopperlayer 51, interlayer dielectric film 52, etching stopper layer 53 (FIG.8(a)).

After that, a hole 54 that pierces through the etching stopper layer 51,the interlayer dielectric film 52 and the etching stopper layer 54 isformed by using a photolithography technique and an etching technique(FIG. 8(b)).

The hole 54 has the same pattern as a via hole 56. Next, aninterconnection trench 55 is formed in the second interconnection layer61 by using a photolithography technique and an etching technique. Atthis time, the pattern of the hole 54 is transferred to the interlayerdielectric film 49 and the via hole 56 is formed (FIG. 8(c)).

(Formation of Barrier Metal)

Ta having a film thickness of 10 to 30 nm is formed as the barrier metallayer 48 by the sputtering method on the whole surface of the substrateincluding the interconnection trench 55 and the via hole 56 (FIG. 8(d)).plating method which involves using a plating liquid containing carbonnanomaterials (fibrous nanomaterials represented by single-layer andmulti-layer/metallic, semiconducting and insulating carbon nanotubesetc., granular carbon nanomaterials represented by carbon nanohorns,fullerenes, etc., and nanomaterials such as a thin silicon wire).

By using the plating method of this embodiment which involves using aplating solution containing carbon nanotubes, it is possible to omit thestep of forming particles and the step of forming carbon nanotubes,which are described in the first to third embodiments.

When copper is used in the trench interconnection structure, it ispossible to use an ordinary copper sulfate-based plating liquid as theplating liquid for this embodiment. For example, a solution obtained bymixing 0.1 m of copper sulfate, 1.0 g/l of carbon nanotubes and asurfactant was used, and before plating, ultrasonic waves were appliedfor 10 minutes so that the carbon nanotubes are sufficiently dispersedin the plating solution. After that, electrolytic plating was performedunder usual conditions. Incidentally, the dispersion by ultrasonic wavesmay be performed during plating.

The content of carbon nanotubes in the plating liquid, which depends onthe content of carbon nanotubes required by the properties of a filmformed by plating, is not less than 0.2 g/l, preferably not less than0.5 g/l, and more preferably not less than 1.0 g/l. When the content isnot less than 0.2 g/l, carbon nanotubes are dispersed in the film. It isnot especially necessary to set an upper limit. However, an upper limitis not more than 25 g/l, preferably not more than 15 g/l, and morepreferably not more than 10 g/l. When the upper limit is not more than25 g/l, carbon nanotubes are uniformly dispersed in the plated film.

Incidentally, although electrolytic plating with copper is exemplifiedin this embodiment, it is possible to perform plating with other metalssuch as gold and silver with which plating is ordinarily performed.

As the electrolytic plating liquid for this embodiment, it isunnecessary to use a plating liquid particular to this embodiment, andit is possible to use commercially available plating liquids.

Furthermore, this embodiment can be adapted also to electroless plating.

Although carbon nanotubes are used as nanomaterials in this embodiment,fibrous nanomaterials represented by single-layer andmulti-layer/metallic, semiconducting and insulating carbon nanotubesetc., granular carbon nanomaterials represented by carbon nanohorns,fullerenes, etc., and nanomaterials such as a thin silicon wire may alsobe used. When an interconnection containing carbon nanotubes is formedby the plating method which involves using a plating liquid containingcarbon nanomaterials (fibrous nanomaterials represented by single-layerand multi-layer/metallic, semiconducting and insulating carbon nanotubesetc., granular carbon nanomaterials represented by carbon nanohorns,fullerenes, etc., and nanomaterials such as a thin silicon wire may beused), this produces a marked effect that voids do not occur in metalfilms formed as an interconnection and a via.

1. A semiconductor device comprising connection plug wherein ananomaterial is substantially uniformly disposed in a section of theconnection plug formed from a metal.
 2. A semiconductor devicecomprising an interconnection wherein a nanomaterial is substantiallyuniformly formed on a bottom surface of the interconnection formed froma metal.
 3. The semiconductor device according to claim 1, wherein thenanomaterial is a fibrous carbon nanomaterial, a particle-like carbonnanomaterial or a thin silicon wire.
 4. The semiconductor deviceaccording to claim 2, wherein the nanomaterial is a fibrous carbonnanomaterial, a granular particle-like carbon nanomaterial or a thinsilicon wire.
 5. The semiconductor device according to claim 1, whereinthe nanomaterial is oriented substantially perpendicularly to asubstrate.
 6. The semiconductor device according to claim 2, wherein thenanomaterial is oriented substantially perpendicularly to a substrate.7. The semiconductor device according to claim 1, wherein thenanomaterial is provided in the whole connection plug.
 8. Thesemiconductor device according to claim 2, wherein the nanomaterial isprovided up to the vicinity of a top surface of the interconnection. 9.The semiconductor device according to claim 1, wherein the metal isformed by an MOCVD method or a plating method.
 10. The semiconductordevice according to claim 2, wherein the metal is formed by an MOCVDmethod or a plating method.
 11. A method of manufacturing asemiconductor device, wherein the method comprises the step of formingparticles of nanometer size on an insulating base, the step of causing ananomaterial to grow on the particles of nanometer size, the step ofdepositing a metal on the substrate on which the nanomaterial has grown,and the step of working the metal including the nanomaterial into aninterconnection.
 12. A method of manufacturing a semiconductor device,wherein the method comprises the step of forming a trench in aninsulating base, the step of forming particles of nanometer size atleast in a bottom portion of the trench, the step of causing ananomaterial to grow on the particles of nanometer size, the step ofdepositing a metal so that the trench is embedded with the metal, andthe step of working the metal including the nanomaterial into aninterconnection.
 13. The method of manufacturing a semiconductor deviceaccording to claim 12, wherein the insulating base has aninterconnection in a lower layer or a device element formed on thesemiconductor substrate and that at least part of the lower-layerinterconnection or the device element is exposed to part of the bottomportion of the trench formed in the insulating base.
 14. The method ofmanufacturing a semiconductor device according to claim 11, wherein theparticles of nanometer size are any of iron, platinum, nickel, cobalt orsilicide substances of nickel and cobalt, and iron oxides.
 15. Themethod of manufacturing a semiconductor device according to claim 12,wherein the particles of nanometer size are any of iron, platinum,nickel, cobalt or silicide substances of nickel and cobalt, and ironoxides.
 16. The method of manufacturing a semiconductor device accordingto claim 11, wherein the nanomaterial is a fibrous carbon nanomaterial,a particle-like carbon nanomaterial or a thin silicon wire.
 17. Themethod of manufacturing a semiconductor device according to claim 12,wherein the nanomaterial is a fibrous carbon nanomaterial, aparticle-like carbon nanomaterial or a thin silicon wire.
 18. The methodof manufacturing a semiconductor device according to claim 11, whereinin the step of depositing a metal, the metal is deposited by a platingmethod or an MOCVD method.
 19. The method of manufacturing asemiconductor device according to claim 12, wherein in the step ofdepositing a metal, the metal is deposited by a plating method or anMOCVD method.
 20. The semiconductor device according to claim 1, whereinthe connection plug formed from a metal is formed by a plating methodwhich involves using a plating liquid containing a nanomaterial.
 21. Thesemiconductor device according to claim 2, wherein the interconnectionformed from a metal is formed by a plating method which involves using aplating liquid containing a nanomaterial.
 22. A method of manufacturinga semiconductor device, wherein the method comprises the step of forminga metal plated film on an insulating base, the metal plated filmcontaining a nanomaterial by using a plating liquid containing thenanomaterial, and the step of working the metal plated film containingthe nanomaterial into an interconnection.
 23. A method of manufacturinga semiconductor device, wherein the method comprises the step of forminga trench in an insulating base, the step of forming a metal plated filmcontaining a nanomaterial by using a plating liquid containing thenanomaterial in such a manner as to embed at least the trench, and thestep of working the metal plated film containing the nanomaterial intoan interconnection.
 24. The method of manufacturing a semiconductordevice according to claim 23, wherein at least part of the lower-layerinterconnection and the device element is exposed to part of a bottomportion of the trench formed on the insulating base.
 25. The method ofmanufacturing a semiconductor device according to claim 22, wherein thenanomaterial is a fibrous carbon nanomaterial, a granular carbonnanomaterial or a thin silicon wire.
 26. The method of manufacturing asemiconductor device according to claim 23, wherein the nanomaterial isa fibrous carbon nanomaterial, a granular carbon nanomaterial or a thinsilicon wire.